Inference Rules

Most object files or executables are made in predictable ways. You can make your makefiles shorter and easier to write by encoding these ways into inference rules.
Here is an example inference rule:
```
.c.o:
	gcc -c -g $*.c
```
Translated, it means that a .c file can be made into a .o file by executing the gcc line. The $*.c is a makefile macro which becomes the file name part of the current dependent with the suffix deleted. For example, if the makefile knew that ctest depended on complex.o but didn't know how to make complex.o, it could use this rule to make it by running gcc -c -g complex.c.
Because of their usefulness, make has a large number of built-in inference rules. For example, here is a built-in rule:
```
.c.o:
        $(CC) $(CFLAGS) -c $*.c
```
The only difference between this rule and our rule is that it uses two makefile macros: CC, and CFLAGS. These default to /bin/cc and nothing, respectively, but can easily be changed:
```
CC = gcc
CFLAGS = -g
```

Here is our previous example, done more succintly:

CC = gcc
OFILES = ctest.o complex.o
ctest : $(OFILES)
	$(CC) $(OFILES) -g -o ctest
$(OFILES) : complex.h